IDEA core
The Temporary Design Result of IDEA Core
1. Designing Asynchronized-clear D Latch
The C Structural Description
/* Asynchronized D latch */
#include
main()
{
DEF_LOFIG("d_latch");
LOCON("d", IN, "d"
);
LOCON("en", IN, "en" );
LOCON("clr", IN, "clr");
LOCON("q", INOUT, "q" );
LOCON("vdd", IN, "vdd");
LOCON("vss", IN, "vss");
LOINS("inv_x2","inv","d","o_inv","vdd","vss",0);
LOINS("a2_x2","an1","o_inv","en","o_an1","vdd","vss",0);
LOINS("a2_x2","an2","d","en","o_an2","vdd","vss",0);
LOINS("no3_x4","nor1","o_an1","clr","o_nor2","q","vdd","vss",0);
LOINS("no2_x4","nor2","q","o_an2","o_nor2","vdd","vss",0);
SAVE_LOFIG();
exit(0);
}
The Test Bench Result of The VHDL Structural Description
-- description generated by Pat driver v107
-- date : Sat Mar 3 03:02:16 2001
-- sequence : d_latch_vbe
-- input / output list :
in vdd B;
in vss B;
in d B;
in en B;
in clr B;
out q B;
begin
-- Pattern description :
--
vvdec q
--
ds nl
--
ds r
path_1
: 10000?u;
path_2
: 10100?u;
path_3
: 10110?1;
path_4
: 10100?1;
path_5
: 10000?1;
path_6
: 10010?0;
path_7
: 10000?0;
path_8
: 10100?0;
path_9
: 10110?1;
path_10
: 10010?0;
path_11
: 10110?1;
path_12
: 10100?1;
path_13
: 10000?1;
path_14
: 10001?0;
path_15
: 10101?0;
path_16
: 10111?0;
path_17
: 10101?0;
path_18
: 10100?0;
path_19
: 10110?1;
path_20
: 10100?1;
end;
2. Designing The Synchronized 16-bit xor
/* the synchronized 16-bit xor */
#include
main()
{
int i;
DEF_LOFIG("s16xor");
LOCON("a[0:15]", IN, "a[0:15]"
);
LOCON("b[0:15]", IN, "b[0:15]"
);
LOCON("en",
IN, "en" );
LOCON("clr",
IN, "clr" );
LOCON("q[0:15]", OUT, "q[0:15]"
);
LOCON("vdd",
IN, "vdd" );
LOCON("vss",
IN, "vss" );
for(i=0;i {
LOINS("xr2_x1",NAME("xr%d",i),NAME("a[%d]",i),NAME("b[%d]",i),NAME("o_xr[%d]",i),"vdd","vss",0);
LOINS("d_latch",NAME("dl%d",i),NAME("o_xr[%d]",i),"en","clr",NAME("q[%d]",i),"vdd","vss",0);
}
SAVE_LOFIG();
exit(0);
}
3. Designing The Fulladder
/* fulladder */
#include
main()
{
DEF_LOFIG("fadder");
LOCON("a", IN, "a"
);
LOCON("b", IN, "b"
);
LOCON("cin", IN, "cin" );
LOCON("cout", OUT, "cout" );
LOCON("sout", OUT, "sout" );
LOCON("vdd", IN, "vdd" );
LOCON("vss", IN, "vss" );
LOINS("halfadder_x2","ha1","a","b","c1","s1","vdd","vss",0);
LOINS("halfadder_x2","ha2","s1","cin","c2","sout","vdd","vss",0);
LOINS("o2_x2","or1","c1","c2","cout","vdd","vss",0);
SAVE_LOFIG();
exit(0);
}
4. Designing The Synchronized modulo 2^16 adder
/* Synchronized modulo 2^16 adder */
#include
main()
{
int i;
DEF_LOFIG("s16adder");
LOCON("a[0:15]", IN, "a[0:15]"
);
LOCON("b[0:15]", IN, "b[0:15]"
);
LOCON("s[0:15]", OUT, "s[0:15]"
);
LOCON("vdd",
IN, "vdd" );
LOCON("vss",
IN, "vss" );
LOINS("halfadder_x2","ha","a[0]","b[0]","c[0]","ss[0]","vdd","vss",0);
LOINS("d_latch","dl0","ss[0]","en","clr","s[0]","vdd","vss",0);
for(i=1;i {
LOINS("fadder",NAME("fa%d",i),NAME("a[%d]",i),NAME("b[%d]",i),NAME("c[%d]",i-1),
NAME("c[%d]",i),NAME("ss[%d]",i),"vdd","vss",0);
LOINS("d_latch",NAME("dl%d",i),NAME("ss[%d]",i),"en","clr",NAME("s[%d]",i),"vdd","vss",0);
}
LOINS("xr2_x1","xr1","a[15]","b[15]","o_xr1","vdd","vss",0);
LOINS("xr2_x1","xr2","o_xr1","c[14]","ss[15]","vdd","vss",0);
LOINS("d_latch","dl15","ss[15]","en","clr","s[15]","vdd","vss",0);
SAVE_LOFIG();
exit(0);
}